Delta Tau NNA1E222.1 UMAC-CPCI PMAC2 Turbo CPU 603625-104

Name: Delta Tau NNA1E222.1 UMAC-CPCI PMAC2 Turbo CPU 603625-104
Brand: Delta Tau Data Systems

Model: NNA1E222.1

Brand Delta Tau Data Systems

Series Pending

Model NNA1E222.1

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Technical Dossier

Product Details And Specifications

Delta Tau UMAC-CPCI Series Technical Notes

The Evolution of UMAC-CPCI Architecture

Delta Tau's motion control lineage begins with the original PMAC (Programmable Multi-Axis Controller) introduced in the early 1990s, which established the foundation for DSP-based multi-axis servo control. The PMAC2 generation introduced a faster Motorola DSP56300-series processor, expanded memory addressing, and a refined servo interrupt structure capable of sub-millisecond loop closure. The UMAC-CPCI chassis was developed to package PMAC2 Turbo intelligence into a 6U CompactPCI rack, enabling modular I/O expansion via standardized CPCI slots. Key architectural milestones include the transition from PMAC1 ISA-bus cards to PMAC2 PCI/CPCI form factors, the introduction of the Turbo PMAC2 with enhanced floating-point DSP throughput, and the subsequent migration path toward the Power PMAC (UMAC-TURBO successor) based on PowerPC architecture. Compatibility considerations are critical: PMAC2 Turbo firmware is not binary-compatible with Power PMAC firmware; motion programs and PLC code require recompilation and logic review when migrating between generations. Legacy UMAC-CPCI systems running PMAC2 Turbo firmware (versions 1.940–1.945) remain in active service at facilities with long equipment replacement cycles, making certified spare parts availability a primary operational concern.

UMAC-CPCI Full Catalog & Functionalities (SKU List)

CPU / Controller Modules

603625-104 (NNA1E222.1): PMAC2 Turbo CPU, UMAC-CPCI main processor, 32-axis capable
603625-101: PMAC2 Turbo CPU, earlier revision, 8-axis base configuration
603625-108: PMAC2 Turbo CPU, extended memory variant for large program storage
603610-101: UMAC-CPCI Turbo PMAC2 CPU with integrated Ethernet option
603610-104: UMAC-CPCI CPU, dual-port RAM interface for host PC communication

Analog / Digital I/O Modules

602804-101: ACC-24E2A – 8-channel ±10V analog output, 16-bit DAC, servo drive interface
602804-102: ACC-24E2S – 8-channel analog output with encoder feedback input
602805-101: ACC-28E – 32-channel digital I/O, 24VDC, opto-isolated
602805-102: ACC-28E2 – 64-channel digital I/O expansion, CPCI slot-mounted
602806-101: ACC-65E – 16-channel analog input, 12-bit ADC, for process feedback

Encoder / Feedback Interface Modules

602803-101: ACC-51E – 8-axis incremental encoder interface, RS-422 differential
602803-102: ACC-51E2 – 8-axis encoder interface with SSI absolute encoder support
602803-104: ACC-51E4 – EnDat 2.2 / Hiperface absolute encoder interface module

Communication & Fieldbus Adapter Modules

602810-101: ACC-84E – PROFIBUS-DP slave adapter for UMAC-CPCI backplane
602811-101: ACC-85E – DeviceNet adapter, scanner/slave configurable
602812-101: ACC-86E – EtherCAT master interface for distributed I/O integration

Power Supply Modules

602800-101: UMAC-CPCI 6U Power Supply, 100–240VAC input, +5V/+12V/-12V regulated DC output
602800-102: UMAC-CPCI Redundant Power Supply module, hot-swap capable

Sourcing Hard-to-Find & Obsolete UMAC-CPCI Parts

The UMAC-CPCI platform entered its mature/end-of-active-production phase as Delta Tau (acquired by Kollmorgen/Danaher) transitioned its primary development focus to the Power PMAC and EtherCAT-native architectures. However, the installed base of UMAC-CPCI systems in long-lifecycle industries — nuclear instrumentation, offshore drilling control, and legacy CNC retrofit — remains substantial. OEM new-production availability for modules such as the 603625-104 and associated ACC-series I/O cards is no longer guaranteed through standard distribution channels.

Quality Control for the UMAC-CPCI Range

UMAC-CPCI modules present specific test challenges due to their CompactPCI backplane bus architecture and real-time DSP servo loop dependencies. DriveKNMS applies a structured validation protocol for all UMAC-CPCI units processed:

Backplane continuity verification: All CPCI J1/J2 connector pins tested for impedance and signal integrity before module insertion.
CPU boot sequence validation: The 603625-104 CPU is powered in a reference UMAC-CPCI chassis; PMAC2 Turbo firmware initialization, DSP clock lock, and DPRAM handshake with host interface are confirmed.
Servo loop closure test: A closed-loop axis test with a reference encoder and simulated motor load verifies PID computation accuracy and interrupt timing.
I/O module functional test: ACC-series analog and digital modules are tested for channel-by-channel output accuracy (DAC linearity ±0.05% FSR) and input threshold response.
Fieldbus adapter enumeration: PROFIBUS and DeviceNet adapters are tested for correct GSD/EDS enumeration and data exchange with a reference master.
Burn-in cycle: All CPU modules undergo a minimum 48-hour powered burn-in at ambient temperature to screen for early-life component failures.

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