FUJI SHARP Z Series Modules Z-312J

Technical Dossier

Product Details And Specifications

FUJI SHARP Z Series Technical Notes

The Evolution of SHARP Z Architecture

The SHARP Z platform was introduced by FUJI Electric as a successor to earlier relay-logic and first-generation PLC installations in Japanese industrial facilities. The initial architecture centered on a fixed-scan CPU with parallel I/O polling, operating over a proprietary backplane bus at TTL logic levels. As the platform matured through successive hardware revisions, FUJI introduced enhanced CPU modules with expanded program memory, floating-point arithmetic support, and structured text compatibility aligned with IEC 61131-3 language standards.

Mid-generation revisions addressed field-reported issues with backplane connector wear under high-vibration conditions, introducing gold-contact edge connectors on I/O modules and revised locking mechanisms on power supply units. Communication capabilities expanded from RS-232C point-to-point links to multi-drop RS-485 and eventually FUJI's proprietary T-Link network, enabling peer-to-peer data exchange between SHARP Z racks without host CPU arbitration.

Compatibility across hardware generations is constrained by backplane bus voltage and slot-addressing schemes. Early-generation I/O modules (Z-3xx series) are not electrically compatible with later Z-4xx backplanes without adapter hardware. Engineers managing mixed-generation installations must verify module revision codes stamped on the PCB edge label, as catalog numbers alone do not distinguish between incompatible hardware revisions. The SHARP Z platform is now classified by FUJI Electric as a mature/end-of-active-production series; replacement recommendations point toward the FUJI MICREX-SX and MICREX-F series for new installations, while the SHARP Z remains supported through authorized spare parts channels for existing plant assets.

SHARP Z Full Catalog & Functionalities (SKU List)

CPU & Controller Modules

• Z-312J: Standard CPU module, 12K-step program memory, RS-232C port, T-Link master capability
• Z-312JA: Enhanced CPU, extended memory addressing, improved scan-time performance over Z-312J baseline
• Z-332J: High-capacity CPU, 32K-step memory, dual-port communication, redundancy-ready architecture
• Z-332JA: Revised Z-332J with expanded data register table and floating-point instruction set
• Z-352J: Top-tier CPU module, 64K-step capacity, structured text support, Ethernet option slot

Digital Input (DI) Modules

• Z-10DI: 16-channel 24VDC digital input, sink/source selectable, LED status per channel
• Z-10DIA: 32-channel 24VDC digital input, high-density format, common return bus
• Z-10DIB: 16-channel 120VAC digital input, optically isolated, DIN-rail mount compatible
• Z-10DIC: 16-channel 240VAC digital input, reinforced isolation, CE/UL rated

Digital Output (DO) Modules

• Z-10DO: 16-channel 24VDC transistor output, 0.5A per channel, short-circuit protected
• Z-10DOA: 16-channel relay output, 2A per channel, Form-C contacts, 250VAC rated
• Z-10DOB: 32-channel transistor output, high-density, shared common per 16-channel group

Analog I/O Modules

• Z-10AI: 8-channel analog input, 4–20mA / 0–10V selectable, 12-bit resolution
• Z-10AO: 4-channel analog output, 4–20mA / 0–10V, 12-bit DAC, loop-powered option
• Z-10AIA: 8-channel high-resolution analog input, 14-bit, thermocouple/RTD compatible with cold-junction compensation

Communication & Network Modules

• Z-10CM: T-Link communication adapter, slave mode, supports up to 64 nodes per segment
• Z-10CMA: RS-485 multi-drop communication module, Modbus RTU master/slave, configurable baud rate
• Z-10CMB: PROFIBUS-DP slave adapter, GSD file provided, 244-byte I/O data exchange

Power Supply Modules

• Z-10PS: 24VDC rack power supply, 5A output, wide-range AC input 85–264VAC, overcurrent protected
• Z-10PSA: Redundant power supply module, hot-swap capable, status relay output for SCADA integration

Quality Control for the SHARP Z Range

SHARP Z modules present specific test challenges due to the proprietary backplane bus protocol and the age-related degradation patterns common in long-installed industrial electronics. DriveKNMS applies the following verification procedures to all SHARP Z inventory:

Backplane Bus Integrity Test: Each module is seated in a SHARP Z test rack and subjected to full backplane communication cycling. CPU modules are verified for correct slot-addressing response and data register read/write integrity across the full address range.

I/O Channel Functional Test: Digital I/O modules are tested channel-by-channel using calibrated signal sources and load banks. Analog modules are verified for linearity, offset error, and gain accuracy against the published specification tolerance (typically ±0.5% full scale).

Visual and Component Inspection: All boards undergo magnified visual inspection for cracked solder joints, corroded traces, swollen electrolytic capacitors, and damaged connector pins — failure modes statistically elevated in modules with 10+ years of field service.