GE DS200 Series Drive Control Boards: DS200SDCCG1AGD & DS215SDCCG1AZZ01B

Technical Dossier

Product Details And Specifications

GE DS200 Series: Comprehensive Drive Control Board Range and Technical Overview

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A: Quantity, required condition, documentation needs, destination and sourcing route are confirmed during RFQ review before quotation.

The DS200SDCCG1AGD is a Speed and Synchronization Control Card used in Mark VI simplex and TMR (Triple Modular Redundant) configurations. The DS215SDCCG1AZZ01B is the DS215-generation equivalent, sharing functional architecture but updated for revised backplane pinout and firmware compatibility within later Mark VI revisions. Both boards handle turbine speed sensing, zero-crossing detection, and synchronization signal processing — functions that are safety-critical and cannot be substituted with non-OEM equivalents without full system re-validation.

The Evolution of DS200 Architecture

GE's turbine control board architecture evolved through three distinct generations, each tied to a major control system platform revision:

Mark V Era (1991–2000): The predecessor DS3800 and DS3820 board families operated on a proprietary serial backplane. These boards used EPROM-based firmware and were not field-upgradeable. Compatibility was strictly tied to the Mark V rack assembly (TCCA, TCCB, TCCC cores). DS3800 boards are now fully obsolete with no OEM support.

Mark VI Era (2000–2012): The DS200 series was introduced as the primary I/O and control board family for the Mark VI system. The architecture shifted to a VME-compatible backplane with IONET and ARCNET communication buses. DS200 boards introduced modular redundancy — individual boards could be replaced in TMR configurations without full system shutdown. Firmware was stored on onboard flash and upgradeable via the Mark VI Toolbox software. This generation includes the DS200SDCCG1AGD and DS215SDCCG1AZZ01B covered on this page.

DS200 Full Catalog & Functionalities (SKU List)

Speed & Synchronization Control

• DS200SDCCG1AGD: Speed/sync control card, Mark VI simplex & TMR, zero-crossing detection
• DS215SDCCG1AZZ01B: DS215-gen speed/sync card, updated backplane pinout, Mark VI late revision
• DS200SDCCG1A: Base revision speed control card, Mark VI simplex configuration

Analog I/O Modules

• DS200IIBDG1A: Analog input board, 16-channel, 4–20 mA / 0–10 V, Mark VI rack mount
• DS200IIBDG1B: Revised analog input board, improved EMI filtering, Mark VI TMR
• DS200AIBDG1ADB: Analog input board with diagnostics, thermocouple & RTD inputs
• DS200AOBDG1A: Analog output board, 8-channel, 4–20 mA output, valve positioner interface

Digital I/O Modules

• DS200DIBBG1A: Digital input board, 24 VDC, 32-channel, contact sensing
• DS200DOEAG1A: Digital output board, relay type, 16-channel, 120 VAC rated
• DS200DOEAG1B: Revised digital output relay board, enhanced contact rating
• DS200DTBCG1A: Digital terminal board, field wiring interface for DI/DO modules

Communication & Network Adapters

• DS200TCQAG1B: ARCNET communication board, Mark VI inter-controller bus interface
• DS200TCQCG1B: Enhanced ARCNET board, dual-port, TMR redundancy support
• DS200EXPSG1A: Ethernet expansion board, IONet interface for Mark VI to Mark VIe bridge

Power Supply & Backplane

• DS200PSDAG1A: Power supply distribution board, 28 VDC regulated, Mark VI rack
• DS200TBQCG1A: Terminal board, quad-channel, field I/O termination for analog loops
• DS215TCQAG1B: DS215-generation ARCNET communication card, Mark VI late-series racks

Quality Control for the DS200 Range

DS200 and DS215 boards undergo a structured test protocol prior to dispatch, designed around the specific failure modes common to Mark VI turbine control hardware:

Backplane Interface Verification: Each board is seated in a Mark VI-compatible test rack and powered through the standard 28 VDC supply rail. Backplane connector pins are inspected under 10x magnification for fretting corrosion — a common failure mode in boards removed from high-vibration turbine enclosures.

ARCNET Bus Communication Test: For communication boards (TCQAG1B, TCQCG1B), ARCNET node addressing and packet transmission are verified using a dedicated bus analyzer. Error rates must be below 0.01% over a 30-minute continuous test cycle.

Analog Channel Calibration: All analog I/O boards are tested across the full 4–20 mA and 0–10 V input/output range. Linearity error must be within ±0.1% of full scale. Thermocouple input boards are tested against NIST-traceable reference sources.

Speed Signal Simulation (SDCC boards): DS200SDCCG1AGD and DS215SDCCG1AZZ01B boards are tested using a turbine speed signal simulator generating 0–3600 RPM equivalent pulse trains. Zero-crossing detection accuracy and synchronization output timing are verified against OEM specification tolerances.